1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and improved process for fabricating a LDMOS (Laterally Diffused MOS transistors) with double LDD (Lightly Doped Drain) and trenched drain structure to provide a low resistance path for the current with enhanced FOM characteristic.
2. The Prior Arts
In U.S. Pat. No. 7,282,765, a LDMOS transistor cell with substrate having a first N semiconductor doping type of prior art was disclosed, as shown in FIG. 1. The transistor cell structure comprises: a highly N+ doped substrate 100 onto which formed a lightly doped epitaxial layer 102 having dopants of N or P dopant type; a body region 104 having P type dopants within which implanted an N+ source region 106; a LDD region 108 formed into epitaxial layer 102 while adjacent to the top surface of said epitaxial layer; a vertical drain contact region 110 where current flows through; a deep trench region 112 for the formation of vertical drain contact region 110 while its open; conductive gate including a doped polysilicon layer 114 and an upper silicide layer 115 formed over a gate dielectric 113; an insulating layer 116 covering the source region 106, the conductive gate sidewalls and its upper surface, and the LDD region 108. The illustrated structure further comprises a shallow trench region 118 by which body region 104 and source region 106 are connected to source metal 119, while a body contact doping region 117 having a dopant concentration P++ greater than the concentration of body region is introduced to reduce the resistance between body region and source metal.
As analyzed in prior art, the LDD region 108 increases the drain-to-source breakdown voltage (BV) of the LDMOS due to its lower doping concentration. However, the low concentration of drain region can not provide a low resistance path for current flow, that means the on resistance between drain and source (Rdson) is large due to low doping concentration in drain region, which will lead to a large conduction loss. Therefore, it is necessary to make a compromise between breakdown voltage and Rdson to optimize the device performance.
Another disadvantage of the prior art is that, there is a high parasitic resistance RL 109 between surface of the LDD region 108 and N+ region 110 connected to bottom of LDD region 108 due to the lower doping concentration, causing high Rdson between drain and source.
Another disadvantage of the prior is that, a parasitic bipolar N+PN in the prior art is easily triggered on due to existence of high base resistance RB 111 underneath source region 106, resulting in device destroy.
Accordingly, it would be desirable to provide a new LDMOS cell structure with low on-resistance between the source region and drain region while sustaining a high breakdown voltage without triggering on the parasitic bipolar.